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1 fn6618.3 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2007-2009, 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. ISL12032 real time clock with 50/60 hz clock and crystal backup low power rtc with battery backed sram and 50/60 cycle ac input and xtal back-up the ISL12032 device is a low power real time clock with 50/60 ac input for timing synchronization. it also has an oscillator utilizing an external crystal for timing back-up, clock/calendar registers, intelligent battery back-up switching, battery voltage moni tor, brownout indicator, integrated trickle charger for super capacitor, single periodic or polled alarms, por superv isory function, and up to 4 event detect with time stam p. there are 128 bytes of battery-backed user sram. the oscillator uses a 50/60 cycle sine wave input, backed by an external, low-cost, 32.768khz crystal. the real time clock tracks time with separate registers for hours, minutes, and seconds. the calendar regist ers contain the date, month, year, and day of the week. the calendar is accurate through year 2100, with automatic leap year correction and auto daylight savings correction. pinout ISL12032 (14 ld tssop) top view features ? 50/60 cycle ac as a primary clock input for rtc timing ? redundant crystal clock input selectable by user - dynamically switch from ac clock input to crystal in case of power failure ? real time clock/calendar - tracks time in hours, minutes, seconds and tenths of a second - day of the week, day, month, and year ? auto daylight saving time correction - programmable forward and backward dates ? security and event functions - event detection with time stamp - stores first and last three event time stamps ? separate f out pin - 7 selectable frequency outputs ? dual alarms with hardware and register indicators - hardware single event or pulse interrupt mode ? automatic backup to batt ery or super capacitor - vbat operation down to 1.8v - 1.0a battery supply current ? two battery status monitors with selectable levels - seven selectable voltages for each level - 1st level, trip points from 4.675v to 2.125v - 2nd level, trip points from 4.125v to 1.875v ?v dd power brownout monitor - six selectable trip levels, from 4.675v to 2.295v ? time stamp during power-to-battery and battery-to-power switchover ? integrated trickle charger - four selectable charging rates ? 128 bytes batter y-backed user sram ?i 2 c interface - 400khz data transfer rate ? pb-free (rohs compliant) applications ? utility meters ? control applications ? security related applications ? vending machines ? white goods ? consumer electronics v dd irq scl sda x1 x2 vbat 1 2 3 4 14 13 12 11 gnd 5 6 7 10 9 8 ac acrdy lv f out evin evdet data sheet may 5, 2011
2 fn6618.3 may 5, 2011 block diagram ordering information part number (notes 1, 2, 3) part marking v dd range temp range (c) package (pb-free) pkg dwg # ISL12032ivz 12032 ivz 2.7v to 5.5v -40 to +85 14 ld tssop m14.173 note: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged pr oducts employ special pb-free material sets , molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std- 020. 3. for moisture sensitivity level (msl), please see device information page for ISL12032 . for more information on msl please see techbrief tb363 . i 2 c interface control logic alarm frequency out rtc divider sda buffer crystal oscillator switch scl buffer sda scl x1 x2 v dd vbat irq internal supply v trip seconds minutes hours day of week date month year user sram control registers registers gnd evin evdet ac ac power quality evaluate ac input buffer acrdy f out lv por/lv compare ISL12032
3 fn6618.3 may 5, 2011 functional pin descriptions pin number symbol description 1 x1 the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768khz quartz crystal. x1 also can be driven directly from a 32.768khz source with no crystal connected. 2 x2 the output of an inverting amplifier and is intended to be connected to one pin of an ex ternal 32.768khz quartz crystal. x2 should be left open when x1 is driven from an external source. 3 vbat battery voltage . this pin provides a backup supply voltage to the dev ice. vbat supplies power to the device in the event that the v dd supply fails. this pin shoul d be tied to ground if not used. 4gnd ground . 5ac ac input . the ac input pin accepts either 50hz of 60hz ac 2.5v p-p sine wave signal. 6lv low voltage detection output/brownout alarm. open drain active low output. 7evin event input - the evin is a logic input pin that is used to det ect an externally monitore d event. when a high signal is present at the evin pin, an ?event? is detected. 8 evdet event detect output. active when evin is triggered. open drain active low output. 9f out frequency output. register selectable frequency clock output. cmos output levels. 10 acrdy ac ready . open drain output. when high, ac input signal is qualified for timing use. 11 sda serial data . sda is a bi-directional pin used to transfer serial data into and out of the device. it has an open drain output and may be wire or?ed with other open drain or open collector outputs. 12 scl serial clock . the scl input is used to clock all se rial data into and out of the device. 13 irq interrupt output. open drain active low output. interrupt output pin to indicate alarm is triggered. 14 v dd power supply. ISL12032
4 fn6618.3 may 5, 2011 absolute maximum rati ngs thermal information voltage on v dd , vbat, scl, sda, acrdy, ac, lv , evdet , evin, irq , f out pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v voltage on x1 and x2 pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.5v esd rating human body model (per mil-std-883 method 3014) . . . . .>2kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>200v thermal resistance (typical, note 4) ja (c/w) 14 ld tssop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c supply voltage (v dd ) . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v supply voltage (vbat) . . . . . . . . . . . . . . . . . . . . . . . . . 1.8v to 5.5v caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 4. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. dc operating characteristics specifications apply for: v dd = 2.7v to 5.5v, t a = -40c to +85c, unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +85c . symbol parameter conditions min (note 13) typ (note 7) max (note 13) units notes v dd main power supply 2.7 5.5 v vbat battery supply voltage 1.8 5.5 v i dd1 supply current v dd = 5v, scl, sda = v dd 27 60 a 6 v dd = 3v, scl, sda = v dd 16 45 a 6 i dd2 supply current (i 2 c communications active) v dd = 5v 43 75 a 5, 8 i dd3 supply current for timekeeping at ac input v dd = 5.5v at t a = +25c, f out disabled 9.0 18.0 a 5, 6 ibat battery supply current vbat = 5.5v at t a = +25c 1.0 1.8 a 5, 11 vbat = 2.7v 0.8 1.2 5, 11 vbat = 1.8v 0.7 1.0 a 5, 11 ibat lkg battery input leakage v dd = 5.5v, vbat = 1.8v trken = 0 100 na i li input leakage current on scl 1 a i lo i/o leakage current on sda 1 a vbat m battery level monitor threshold v dd = 5.5v, vbat = 1.8v -150 +150 mv v pbm brownout level monitor threshold -150 +150 mv v trip vbat mode threshold 2.0 2.2 2.4 v v triphys v trip hysteresis 30 mv vbat hys vbat hysteresis 50 mv rtrk trickle charge resistance v dd = 5.5v, vbat = 3.0v, trkr01 = 0, trkr00 = 0 1300 v dd = 5.5v, vbat = 3.0v, trkr01 = 0, trkr00 = 1 2200 v dd = 5.5v, vbat = 3.0v, trkr01 = 1, trkr00 = 0 3600 v dd = 5.5v, vbat = 3.0v, trkr01 = 1, trkr00 = 1 7800 vtrkterm vbat charging termination point vdd - 50mv v ISL12032
5 fn6618.3 may 5, 2011 vtrkhys trickle charge on-off hysteresis 50 mv irq /acrdy/lv /evdet (open drain outputs) v ol output low voltage v dd = 5v, i ol = 3ma 0.4 v v dd = 2.7v, i ol = 1ma 0.4 v f out (cmos output) v ol output low voltage i oh = 1ma 0.3 x v dd v v oh output high voltage 0.7 x v dd v evin i evpu evin pull-up current v dd = 5.5v, vbat = 3.0v 1.0 3.0 8.0 a v dd = 0v, vbat = 1.8v 100 600 na v il input low voltage 0.3 x v dd v v ih input high voltage 0.7 x v dd v i evpd evin disabled pull-down current v dd = 5.5v 200 na dc operating characteristics specifications apply for: v dd = 2.7v to 5.5v, t a = -40c to +85c, unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +85c . (continued) symbol parameter conditions min (note 13) typ (note 7) max (note 13) units notes power-down timing specifications apply for: v dd = 2.7v to 5.5v, t a = -40c to +85c, unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +85c . symbol parameter conditions min (note 13) typ (note 7) max (note 13) units notes v dd sr- v dd negative slew rate 10 v/ms 9 i 2 c interface specifications specifications apply for: v dd = 2.7v to 5.5v, t a = -40c to +85c, unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +85c . symbol parameter test conditions min (note 13) typ (note 7) max (note 13) units notes v il sda and scl input buffer low voltage -0.3 0.3 x v dd v v ih sda and scl input buffer high voltage 0.7 x v dd v dd + 0.3 v hysteresis sda and scl input buffer hysteresis 0.05 x v dd v v ol sda output buffer low voltage, sinking 3ma v dd = 5v, i ol = 3ma 0.4 v c pin sda and scl pin capacitance t a = +25c, f = 1mhz, v dd =5v, v in =0v, v out =0v 10 pf f scl scl frequency 400 khz t in pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed. 50 ns t aa scl falling edge to sda output data valid scl falling edge crossing 30% of v dd , until sda exits the 30% to 70% of v dd window. 900 ns t buf time the bus must be free before the start of a new transmission sda crossing 70% of v dd during a stop condition, to sda crossing 70% of v dd during the following start condition. 1300 ns ISL12032
6 fn6618.3 may 5, 2011 t low clock low time measured at the 30% of v dd crossing. 1300 ns t high clock high time measured at the 70% of v dd crossing. 600 ns t su:sta start condition setup time scl rising edge to sda falling edge. both crossing 70% of v dd . 600 ns t hd:sta start condition hold time from sda falling edge crossing 30% of v dd to scl falling edge crossing 70% of v dd . 600 ns t su:dat input data setup time from sda exiting the 30% to 70% of v dd window, to scl rising edge crossing 30% of v dd. 100 ns t hd:dat input data hold time from scl falling edge crossing 30% of v dd to sda entering the 30% to 70% of v dd window. 0 900 ns t su:sto stop condition setup time from scl rising edge crossing 70% of v dd , to sda rising edge crossing 30% of v dd . 600 ns t hd:sto stop condition hold time from sda rising edge to scl falling edge. both crossing 70% of v dd . 600 ns t dh output data hold time from scl falling edge crossing 30% of v dd , until sda enters the 30% to 70% of v dd window. 0 ns t r sda and scl rise time from 30% to 70% of v dd. 20 + 0.1 x cb 300 ns 10, 12 t f sda and scl fall time from 70% to 30% of v dd. 20 + 0.1 x cb 300 ns 10, 12 cb capacitive loading of sda or scl total on-chip and off-chip 10 400 pf 10, 12 r pu sda and scl bus pull-up resistor off-chip maximum is determined by t r and t f . for cb = 400pf, max is about 2k . for cb = 40pf, max is about 15k 1 k 10, 12 notes: 5. irq and f out inactive. 6. v dd > vbat +v bathys 7. specified at t a =+25c. 8. f scl = 400khz. 9. in order to ensure proper timekeeping, the v dd sr- specification must be followed. 10. parameter is not 100% tested. 11. v dd = 0v. i bat increases at v dd voltages between 0.5v and 1.5v. 12. these are i 2 c specific parameters and are not tested, however, they are used to set conditions for testing dev ices to validate specificatio n. 13. compliance to datasheet limits is assured by one or mo re methods: production test, characterization and/or design. i 2 c interface specifications specifications apply for: v dd = 2.7v to 5.5v, t a = -40c to +85c, unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +85c . (continued) symbol parameter test conditions min (note 13) typ (note 7) max (note 13) units notes ISL12032
7 fn6618.3 may 5, 2011 sda vs scl timing symbol table t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance figure 1. standard output load for testing the device with v dd = 5.0v sda and irq /f out 1533 100pf 5.0v for v ol = 0.4v and i ol = 3ma equivalent ac output load circuit for v dd = 5v ISL12032
8 fn6618.3 may 5, 2011 general description the ISL12032 device is a low power real time clock with 50/60 ac input for timing synchronization. it also has an oscillator utilizing an external crystal for timing back-up, clock/calendar registers, intelligent battery back-up switching, battery voltage moni tor, brownout indicator, integrated trickle charger for super capacitor, single periodic or polled alarms, por superv isory function, and up to 4 event detect with time stam p. there are 128 bytes of battery-backed user sram. the oscillator uses a 50/60 cycle sine wave input, backed by an external, low-cost, 32.768khz crystal. the real time clock tracks time with separate registers for hours, minutes, and seconds. the calendar regist ers contain the date, month, year, and day of the week. the calendar is accurate through year 2100, with automatic leap year correction and auto daylight savings correction. the ISL12032?s alarm can be set to any clock/calendar value for a match. each alarm?s status is available by checking the status register. the device also can be configured to provide a hardware interrupt via the irq pin. there is a repeat mode for the alarms allowing a periodic interrupt every minute, every hour, every day, etc. the device also offers a backup power input pin. this vbat pin allows the device to be backed up by battery or super capacitor with automatic switchover from v dd to vbat. the ISL12032 devices are specified for v dd = 2.7v to 5.5v and the clock/calendar portion of the device remains fully operational in battery backup mode down to 1.8v (standby mode). the vbat level is monitored and warnings are reported against preselected levels. the first report is registered when the vbat level falls below 85% of nominal level, the second level is set for 75% of nominal level. battery levels are stored in the pwrbat registers. the ISL12032 offers a ?brownout? alarm once the v dd falls below a pre-selected trip level. in the ISL12032, this allows the system microcontroller to save vital information to memory before complete po wer loss. there are six v dd trip levels for the brownout alarm. the event detection function ac cepts a normally low logic input, and when triggered will store the time/date information for the event. the first event is stored in the memory until reset; subsequent events are stored on-chip memory and the last 3 events are retained and accessible by performing an indexed register read. pin descriptions x1, x2 the x1 and x2 pins are the input and output, respectively, of an inverting amplifier. an external 32.768khz quartz crystal is used with the device to supply a backup timebase for the real time clock if there is no ac input. the device also can be driven directly from a 32.768khz source at pin x1, in which case, pin x2 should be left unconnected. no external load capacitors are needed for the x1 and x2 pins. vbat (battery input) this input provides a backup supply voltage to the device. vbat supplies power to the device in the event that the vdd supply fails. this pin can be connected to a battery, a super capacitor or tied to ground if not used. ac (ac input) the ac input is the main clock input for the real time clock. it can be either 50hz or 60hz, sine wave. the preferred amplitude is 2.5v p-p , although amplitudes >0.25v dd are acceptable. an ac coupled (series capacitor) sine wave clock waveform is desired as the ac clock input provides dc biasing. lv (low voltage) this pin indicates the vdd supply is below the programmed level. this signal notifies a host processor that the main supply is low and requests action. it is an open drain active low output. evin (event input) the evin pin input detects an externally monitored event. when a high signal is present at the evin pin, an ?event? is detected.this input may be used for various monitoring functions, such as the open ing of a detection switch on a chassis or door. the event detection circuit can be user enabled or disabled (see evin bit) and provides the option to be operational in battery backup modes (see evatb bit). when the event detection is di sabled, the evin pin is gated off. see ?functional pin descriptions? on page 3 for more details. evdet (event detect output) the evdet is an open drain output, which will go low when an event is detected at the evi n pin. if the event detection function is enabled, the evdet output will go low and stay there until the evt bit is cleared. figure 2. recommended crystal connection x1 x2 ISL12032
9 fn6618.3 may 5, 2011 irq (interrupt output) this pin provides an interrupt signal output. this signal notifies a host processor that an alarm has occurred and requests action. it is an open drain active low output. f out (frequency output) this pin outputs a clock signal, which is related to the crystal frequency. the frequency output is user selectable and enabled via the i 2 c bus. the options include seven different frequencies or disable. it is a cmos output. serial clock (scl) the scl input is used to clock all serial data into and out of the device. the input buffer on this pin is always active (not gated). it is disabled when the backup power supply on the vbat pin is activated to minimize power consumption. serial data (sda) sda is a bi-directional pin used to transfer data into and out of the device. it has an open drain output and may be or?ed with other open drain or open co llector outputs. the input buffer is always active (not gated) in normal mode. an open drain output requires the use of a pull-up resistor. the output circuitry controls the fa ll time of the output signal with the use of a slope contro lled pull-down. the circuit is designed for 400khz i 2 c interface speeds. it is disabled when the backup power supply on the vbat pin is activated. v dd , gnd chip power supply and ground pins. the device will operate with a power supply from v dd = 2.7v to 5.5vdc. a 0.1f capacitor is recommended on the v dd pin to ground. functional description power control operation the power control circuit accepts a v dd and a vbat input. many types of batteries can be used with intersil rtc products. for example, 3.0v or 3.6v lithium batteries are appropriate, and battery sizes are available that can power the ISL12032 for up to 10 years. another option is to use a super capacitor for applications where v dd is interrupted for up to a month. see the ?application section? on page 24 for more information. normal mode (v dd ) to battery backup mode (vbat) to transition from the v dd to vbat mode, both of the following conditions must be met: condition 1: v dd < vbat - v bathys where v bathys 50mv condition 2: v dd < v trip where v trip 2.2v battery backup mode (vbat) to normal mode (v dd ) the ISL12032 device will switch from the vbat to v dd mode when one of the following conditions occurs: condition 1: v dd > vbat + v bathys where v bathys 50mv condition 2: v dd > v trip + v triphys where v triphys 30mv these power control situations are illustrated in figures 3 and figure 4. the i 2 c bus is normally deactivated in battery backup mode to reduce power consumption, but can be enabled by setting the i 2 cbat bit. all the other inputs and outputs of the ISL12032 are active during battery backup mode unless disabled via the control register. power failure detection the ISL12032 provides a real time clock failure bit (rtcf) to detect total power failure. it allows users to determine if the device has powered up after having lost all power to the device (both v dd and vbat very near 0.0vdc). note that in cases w here the vbat input is at 0.0v and the v dd input dips to <1.8v, then recovers to normal level, the sram registers ma y not retain their values (corrupted bits or bytes may result). vbat - v bathys vbat vbat + v bathys battery backup mode v dd v trip 2.2v 1.8v figure 3. battery switchover when vbat < v trip figure 4. battery switchover when vbat > v trip v trip vbat v trip + v triphys battery backup mode v dd v trip 3.0v 2.2v ISL12032
10 fn6618.3 may 5, 2011 brownout detection the ISL12032 monitors the v dd level continuously and provides a warning if the v dd level drops below prescribed levels. there are six levels that can be selected for the trip level. these values are 85% below popular v dd levels. the lvdd bit in the srdc register will be set to ?1? when brownout is detected. note that the i 2 c serial bus remains active until the battery v trip level is reached. battery level monitor the ISL12032 has a built in warning feature once the vbat battery level drops first to 85% and then to 75% of the battery?s nominal vbat level. when the battery voltage falls to between 85% and 75%, the lbat85 bit is set in the srdc register. when the level drops below 75%, both lbat85 and lbat75 bits are set in the srdc register. the trip levels for the 85% and 75% levels are set using the pwrbat register. the battery timestamp function permits recovering the time/date when v dd power loss occurre d. once the v dd is low enough to enable switchover to the battery, the rtc time/date are written into the tsv2b section. if there are multiple power-down cycles befor e reading these registers, the first values stored in thes e registers will be retained and ensuing events will be ignored. these registers will hold the original power-down value until they are cleared by writing ?00h? to each register or setting the clrts bit to ?1?. the v dd timestamp function permits recovering the time/date when v dd recovery occurred. once the v dd is high enough to enable switchover to v dd , the rtc time/date are written into the tsb2v register. if there are multiple power-down cycles before reading these registers, the most recent event is retained in these registers and the previous events will be ignored. these registers will hold the original power-down value until they are cleared by writing ?00h? to each register. real time clock operation the real time clock (rtc) main tains an accura te internal representation of tenths of a second, second, minute, hour, day of week, date, month, and year. the rtc also has leap- year correction. the clock al so corrects for months having fewer than 31 days and has a bit that controls 24 hour or am/pm format. when the ISL12032 powers up after the loss of both v dd and vbat, the clock will not begin incrementing until at least one byte is wr itten to the clock register. alarm operation the alarm mode is enabled via the msb bit. single event or interrupt alarm mode is selected via the im bit. the standard alarm allows for alarms of time, date, day of the week, month, and year. when a time alarm occurs in single event mode, the irq pin will be pulled low and the corresponding alarm status bit (alm0 or alm1) will be set to ?1?. the status bits can be written with a ?0? to clear, or if the arst bit is set, a single read of the srdc status register will clear them. the pulsed interrupt mode (setting the im bit to ?1?) activates a repetitive or recurring alarm. hence, once the alarm is set, the device will continue to out put a pulse for each occurring match of the alarm and present time. the alarm pulse will occur as often as every minute (i f only the nth second is set) or as infrequently as once a year (if at least the nth month is set). during pulsed interrupt mode, the irq pin will be pulled low for 250ms and the alarm status bit (alm0 or alm1) will be set to ?1?. the alarm function is not available during battery backup mode. frequency output mode the ISL12032 has the option to provide a clock output signal using the f out cmos output pin. the frequency output mode is set by using the fo bits to select 7 possible output frequency values from 1.0hz to 32.768khz, and disable. the frequency output can be enabled/disabled during battery backup mode by setting the foba tb bit to ?0?. when the ac input is qualified (within the pa rameters of ac qualification) then the frequency output fo r values 50/60hz and below are derived from the ac input clock. higher frequency f out values are derived from the crystal. if the ac clock input is not qualified, then all f out values are derived from the crystal. general purpose user sram the ISL12032 provides 128 bytes of user sram. the sram will continue to operate in battery backup mode. however, it should be noted that the i 2 c bus is disabled in battery backup mode unless enabled by the i 2 cbat bit. i 2 c serial interface the ISL12032 has an i 2 c serial bus interface that provides access to the control and status registers and the user sram. the i 2 c serial interface is compatible with other industry i 2 c serial bus protocols using a bi-directional data signal (sda) and a clock signal (scl). the i 2 c bus normally operates down to the v dd trip point set in the pwrvdd register. it can also operate in battery backup mode by setting the i2cb at bit to ?1?, in which case operation will be down to vbat = 1.8v. register descriptions the battery-backed registers are accessible following an i 2 c slave byte of ?1101 111x? and reads or writes to addresses [00h:47h]. the defin ed addresses and default values are described in the table 1. the battery backed general purpose sram has a different slave address (1010 111x), so it is not possible to read/write that section of memory while accessing the registers. ISL12032
11 fn6618.3 may 5, 2011 register access the contents of the register s can be modified by performing a byte or a page write operation directly to any register address. the registers are divided into 10 sections. they are: 1. real time clock (8 bytes): address 00h to 07h. 2. status (2 bytes): address 08h to 09h. 3. counter (2 bytes): address ah to bh. 4. control (9 bytes): 0ch to 14h. 5. day light saving time (8 bytes): 15h to 1ch 6. alarm 0/1 (12 bytes): 1dh to 28h 7. time stamp for battery status (5 bytes): address 29h to 2dh. 8. time stamp for vdd status (5 bytes): address 2eh to 32h. 9. time stamp for event status (5 bytes): 33h to 37h. write capability is allowable into the rtc registers (00h to 07h) only when the wrtc bit (bit 6 of address 0ch) is set to ?1?. other sections do not need to have the wrtc bit set for write access. a read or write can begin at any address within the section. a write to sections 2 through 9 can be continuous. a write can overl ap two or more sections as well. a register can be read by performing a random read at any address at any time. this returns the contents of that register location. additional registers are read by performing a sequential read. for the rtc and alarm registers, the read instruction latches all clock registers into a buffer, so an update of the clock does not change the time being read. at the end of a read, the master supplies a stop condition to end the operation and free the bus. after a read, the address remains at the previous addre ss +1 so the user can execute a current address read and continue reading the next register. it is only necessary to set the wrtc bit prior to writing into the rtc registers. all other registers are completely accessible without setting the wrtc bit. ISL12032
12 fn6618.3 may 5, 2011 table 1. register memory map (x indicates writes to these bits have no effect on the device) addr section reg name bit range default 76543210 00h rtc sc 0 sc22 sc21 sc20 sc13 sc12 sc11 sc10 0 to 59 00h 01h mn 0 mn22 mn21 mn20 mn13 mn12 mn11 mn10 0 to 59 00h 02h hr mil 0 hr21 hr20 hr13 hr12 hr11 hr10 0 to 23 00h 03h dt 0 0 dt21 dt20 dt13 dt12 dt11 dt10 1 to 31 01h 04h mo 0 0 0 mo20 mo13 mo12 mo11 mo10 1 to 12 01h 05h yr yr23 yr22 yr21 yr20 yr13 yr12 yr11 yr10 0 to 99 00h 06h dw00000dw2dw1dw00 to 600h 07h ss0000ss3ss2ss1ss00 to 900h 08h status srdc bmode dstadj alm1 alm0 lvdd lbat85 lbat75 rtcf n/a 01h 09h srac x x x xoscf x x acfail acrdy n/a 00h 0ah counter accnt axc7 axc6 axxc5 axc4 axc3 axc2 axc1 axc0 0 to 127 00h 0bh evtcnt evc7 evc6 evc5 evc4 evc3 evc2 evc1 evc0 0 to 127 00h 0ch control int arst wrtc im x x x ale1 ale0 n/a 01h 0dh fo x x x fobatb x fo2 fo1 fo0 n/a 00h 0eh evic x evbatb evim even ehys1 ehys0 esmp1 esmp0 n/a 00h 0fh evixxxxxx0evix1evix0n/a00h 10h trickxxxxxtrkentrkro1trkro0n/a00h 11h pwrvdd clrts x i2cbat lvenb x vddtrip2 vddtrip1 vddtrip0 n/a 00h 12h pwrbat x bhys vb85tp2 vb85tp1 vb85tp0 bv75tp2 vb75tp1 vb75tp0 n/a 00h 13h ac ac5060 acenb acrp1 acrp0 acfp1 acfp0 acfc1 acfc0 n/a 00h 14h ftr x x x acmin xdtr3 xdtr2 xdtr1 xdtr0 n/a 00h 15h dstcr dstmofd dste 0 0 mofd20 mofd13 mofd12 mofd11 mofd10 1 to 12 04h 16h dstdwfd 0 dwfde wkfd12 wkfd11 wkfd10 dwfd12 dwfd11 dwfd10 0 to 6 00h 17h dstdtfd 0 0 dtfd21 dtfd20 dtfd13 dtfd12 dtfd11 dtfd10 1 to 31 01h 18h dsthrfd hrfdmil 0 hrfd21 hrfd20 hrfd13 hrfd12 hrfd11 hrfd10 0 to 23 02h 19h dstmorv 0 0 0 morv20 morv13 morv12 morv11 morv10 1 to 12 10h 1ah dstdwrv 0 dwrve wkrv12 wkrv11 wkrv10 dwrv12 dwrv11 dwrv10 0 to 6 00h 1bh dstdtrv 0 0 dtrv21 dtrv20 dtrv13 dtrv12 dtrv11 dtrv10 1 to 31 01h 1ch dsthrrv hrrvmil 0 hrrv21 hrrv20 hrrv 13 hrrv12 hrrv11 hrrv10 0 to 23 02h 1dh alarm0 sca0 esca0 sca022 sca021 sca020 sca013 sca012 sca011 sca010 0 to 59 00h 1eh mna0 emna0 mna021 mna020 mna013 mna012 mna011 mna011 mna010 0 to 59 00h 1fh hra0 ehra0 0 hra021 hra020 hra013 hra012 hra011 hra010 0 to 23 00h 20h dta0 edta0 0 dta021 dta020 dta013 dta012 dta011 dta010 1 to 31 01h 21h moa0 emoa0 0 0 moa020 moa013 moa012 moa011 moa010 1 to 12 01h 22h dwa0 edwa0 0 0 0 0 dwa02 dwa01 dwa00 0 to 6 00h ISL12032
13 fn6618.3 may 5, 2011 real time clock registers addresses [00h to 07h] rtc registers (sc, mn, hr, dt, mo, yr, dw, ss) these registers depict bcd representations of the time. as such, sc (seconds) and mn (minutes) range from 0 to 59, hr (hour) can be either 12-hour or 24-hour mode, dt (date) is 1 to 31, mo (month) is 1 to 12, yr (year) is 0 to 99, dw (day of the week) is 0 to 6, and ss (sub-second) is 0 to 9. the sub- second register is read-only an d will clear to ?0? count each time there is a write to a register in the rtc section. the dw register provides a day of the week status and uses three bits dw2 to dw0 to represent the seven days of the week. the counter advances in the cycle 0-1-2-3-4-5-6-0-1- 2.... the assignment of a numerica l value to a specific day of the week is arbitrary and may be decided by the system software designer. the default value is defined as ?0?. 24 hour time if the mil bit of the hr register is ?1?, the rtc uses a 24-hour format. if the mil bit is ?0?, the rtc uses a 12-hour format and hr21 bit functions as an am/pm indicator with a ?1? representing pm. the clock defaults to 12-hour format time with hr21 = ?0?. leap years leap years add the day february 29 and are defined as those years that are divisible by 4. y ears divisible by 100 are not leap years, unless they are also divi sible by 400. this means that the year 2000 is a leap year and the year 2100 is not. the ISL12032 does not correct for the leap year in the year 2100. status registers (sr) addresses [08h to 09h] the status registers consist of the dc and ac status registers (see tables 2 and 3). status register (srdc) the status register dc is located in the memory map at address 08h. this is a volatile r egister that provides status of rtc failure (rtcf), batter y level monitor (lbat85, lbat75), v dd level monitor (lvdd), alarm0 or alarm1 trigger, daylight saving time adjustment, and battery active mode. 23h alarm1 sca1 esca1 sca122 sca121 sca120 sca113 sca112 sca111 sca110 0 to 59 00h 24h mna1 emna1 mna122 mna121 mna120 mna113 mna112 mna111 mna110 0 to 59 00h 25h hra1 ehra1 0 hra121 hra120 hra113 hra112 hra111 hra110 0 to 23 00h 26h dta1 edta1 0 dta121 dta120 dta113 dta112 dta111 dta110 1 to 31 01h 27h moa1 emoa1 0 0 moa120 moa113 moa112 moa111 moa110 1 to12 01h 28h dwa1 edwa1 0 0 0 0 dwa12 dwa11 dwa10 0 to 6 00h 29h tsv2b scvb x scbv22 scbv21 scbv20 scvb13 scvb12 scvb11 scvb10 0 to 59 00h 2ah mnvb x mnvb22 mnvb21 mnvb20 mnvb13 mnvb12 mnvb11 mnvb10 0 to 59 00h 2bh hrvb milvb x hrvb21 hrvb20 hrvb13 hrvb12 hrvb11 hrvb10 0 to 23 00h 2ch dtvb x x dtvb21 dtvb20 dtvb13 dtvb12 dtvb11 dtvb10 1 to 31 00h 2dh movb x x x movb20 movb13 movb12 movb11 movb10 1 to 12 00h 2eh tsb2v scbv x scbv22 scbv21 scbv20 scbv13 scbv12 scbv11 scbv10 0 to 59 00h 2fh mnbv x mnbv22 mnbv21 mnbv20 mnbv13 mnbv12 mnbv11 mnbv10 0 to 59 00h 30h hrbv milbv x hrbv21 hrbv20 hrbv13 hrbv12 hrbv11 hrbv10 0 to 23 00h 31h dtbv x x dtbv21 dtbv20 dtbv13 dtbv12 dtbv11 dtbv10 1 to 31 00h 32h mobv x x x mobv20 mobv13 mobv12 mobv11 mobv10 1 to 12 00h 33h tsevt sct x sct22 sct21 sct20 sct13 sct12 sct111 sct10 0 to 59 00h 34h mnt x mnt22 mnt21 mnt20 mnt13 mnt12 mnt11 mnt10 0 to 59 00h 35h hrt milt x hrt21 hrt20 hrt13 hrt12 hrt11 hrt10 0 to 23 00h 36h dtt x x dtt21 dtt20 dtt13 dtt12 dtt11 dtt10 1 to 31 00h 37h mot x x x mot20 mot13 mot12 mot11 mot10 1 to 12 00h table 1. register memory map (x indicates writes to these bits have no effect on the device) (continued) addr section reg name bit range default 76543210 ISL12032
14 fn6618.3 may 5, 2011 battery active mode (bmode) bmode indicates that the device is operating from the vbat input. a ?1? indicates battery mode and a ?0? indicates power from v dd mode. the i2cbat bit must be set to ?1? and the device must be in vbat mode in order for a valid ?1? read from this bit. daylight saving time adjustment bit (dstadj) dstadj is the daylight savi ng time adjustment bit. it indicates that daylight sa ving time adjustment has happened. the bit will be set to ?1? when the forward dst event has occurred. the bit will stay set until the reverse dst event has happened. the bit will also reset to ?0? when the dste bit is set to ?0? (dst function disabled). the bit can be forced to ?1? with by writing ?f0h? to the status register. the default value for dstadj is ?0?. alarm bits (alm0 and alm1) these bits announce if an alarm matches the real time clock. if there is a match, the respective bit is set to ?1?. this bit can be manually reset to ?0? by the user or aut omatically reset by enabling the auto-reset bit (see arst bit). a write to this bit in the sr can only set it to ?0?, not ?1?. an alarm bit that is set by an alarm occurring during an sr read operation will remain set after the read operation is complete. low v dd indicator bit (lvdd) indicates v dd dropped below the pre-selected trip level. (brownout mode). the trip points for brownout levels are selected by three bits vddtrip2, vddtrip1 and vddtrip0 in the pwrvdd registers. low battery indicato r 85% bit (lbat85) indicates battery level dropped below the pre-selected trip level (85% of battery voltage). the trip point is set by three bits: vb85tp2, vb85tp1 and vb85tp0 in the pwrbat register. low battery indicato r 75% bit (lbat75) indicates battery level dropped below the pre-selected trip level (75% of battery voltage). the trip point is set by three bits: vb75tp2, vb75tp1 and vb75tp0 in the pwrbat register. real time clock fail bit (rtcf) this bit is set to a ?1? after a total power failure. this is a read only bit that is set by hardw are (internally) when the device powers up after having lost all power (defined as v dd = 0v and vbat = 0v). the bit is set regardless of whether v dd or vbat is applied first. the loss of only one of the supplies does not set the rtcf bit to ?1?. the first valid write to the rtc section after a complete power failure resets the rtcf bit to ?0? (writing one byte is sufficient). status register (srac) the status register ac is located in the memory map at address 09h. this is a volatile r egister that provides status of crystal failure (xoscf), ac failed (acfail) and ac ready (acrdy). crystal oscillator fail bit (xoscf) indicates crystal oscillator has stopped if xoscf = 1. when the crystal oscillator has resumed operation, the xoscf bit is reset to ?0?. ac fail (acfail) this bit announces the status of the ac input. if acfail = 1, then the ac input frequency and amplitude qualification check has failed. acfail is reset to ?0? when the ac input meets the preset requirements (see ?ac (ac input)? on page 8). ac ready (acrdy) this bit announces the status of the ac input. if acrdy = 1, then the ac input has passed the qualification parameter check (as set by acfc and acfp bits) for the time prescribed by acrp and is used for the rtc clock. when acrdy = 0 the ac input failed the qualification requirements and the crystal oscillator clock is used for the rtc clock (see ?ac (ac input)? on page 8). when acfail transitions from ?1? to ?0? (from failed to pass), then the timer set by acrp will determine the delay until acrdy transitions from ?0? to ?1?. acrdy will be set to ?0? immediately after acrdy is set to ?0? (failed ac input), indicating the crystal oscillator is the rtc clock. counter registers addresses [0ah to 0bh] these registers will count the number of times ac failure occurs and the number of times an event occurs. these registers are 8-bits each and will count up to 255. ac count (accnt) the accnt register increments automatically each time the ac input switches to the crystal backup. the register is set to 00h on initial power-up. the maximum count is 255, and will stay at that value until set to zero via an i 2 c write. table 2. status register dc (srdc) addr 7 6 5 4 3 2 1 0 08h bmode dstadj alm1 alm0 lvdd lbat85 lbat75 rtcf table 3. status register ac (srac) addr 7 6 5 4 3 2 1 0 09h x x x xoscf x x acfail acrdy table 4. ac counter register (accnt) addr 7 6 5 4 3 2 1 0 0ah axc7 axc6 axc5 axc4 axc3 axc2 axc1 axc0 ISL12032
15 fn6618.3 may 5, 2011 event count (evtcnt) the evtcnt register increments automatically each time an event occurs. the register is set to 00h on initial power-up. the maximum count is 255, and will stay at that value until set to zero via an i 2 c write. performing a write of 00h to this register will clear the contents of this register and a ll levels of the tsevt section. a clear to this register should be done with care. write event index register zero only selects first event time stamp. write event count evntcnt zero will both clear event counter and all time stamps. control registers addresses [0ch to 14h] the control registers (int , fo, evic, evix, trick, pwrvdd, pwrbat, ac, and ftr) contain all the bits necessary to control the parametric functions on the ISL12032. interrupt control register (int) automatic reset bit (arst) this bit enables/disables the automatic reset of the alm0, alm1, lvdd, lbat85, and lbat75 status bits only. when arst bit is set to ?1?, these status bits are reset to ?0? after a valid read of the srdc register (with a valid stop condition). when the arst is cleared to ?0?, the user must manually reset the alm0, alm1, lvdd, lbat85, and lbat75 bits. write rtc enable bit (wrtc) the wrtc bit enables or disables write capability into the rtc register section. the factory default setting of this bit is ?0?. upon initialization or power-up, the wrtc must be set to ?1? to enable the rtc. upon the completion of a valid write (stop), the rtc starts counting. the rtc internal 1hz signal is synchronized to the stop condition during a valid write cycle. this bit will rema in set until reset to ?0? or a complete power-down occurs (v dd = vbat = 0.0v) alarm interrupt mode bit (im) this bit enables/disables the interrupt mode of the alarm function. when the im bit is set to ?1?, the alarms will operate in the interrupt mode, where an active low pulse width of 250ms will appear at the irq pin when the rtc is triggered by either alarm as defined by the alarm0 section (1dh to 22h) or the alarm1 section (23h to 28h). when the im bit is cleared to ?0?, the alarm will operate in standard mode, where the irq pin will be set low until both the alm0/alm1 status bits are cleared to ?0?. alarm 1 (ale 1) this bit enables the alarm1 function. when ale1 = ?1?, a match of the rtc section with t he alarm1 section will result is setting the alm1 status bit to ?1? and the irq output low. when set to ?0?, the alarm1 function is disabled. alarm 0 (ale 0) this bit enables the alarm0 function. when ale0 = 1, a match of the rtc section with t he alarm1 section will result is setting the alm0 status bit to ?1? and the irq output low. when set to ?0?, the alarm0 function is disabled. frequency out register (fo) frequency output and interrupt bit (fobatb) this bit enables/disables f out during battery backup mode (i.e. vbat power source active). when the fobatb is set to ?1? the f out pin is disabled during battery backup mode. when the fobatb is cleared to ?0?, the f out pin is enabled during battery backup mode (default). note that f out is a cmos output and needs no pull-up resistor. note also that battery current drain will be higher with f out enabled in battery backup mode. frequency out control bits (fo <2:0>) these bits enable/disable the frequency output function and select the output frequency at the f out pin. see table 8 for frequency selection. note t hat frequencies from 4096hz to 32768hz are derived from the crystal oscillator, and the 1.0, 10, and 50/60hz frequencies are derived from the ac clock input. the exception to this is when the ac input qualification has failed, and the crystal oscillator is used for the 1.0hz f out . table 5. event counter register (evtcnt) addr 7 6 5 4 3 2 1 0 0bh evc7 evc6 evc5 evc4 evc3 evc2 evc1 evc0 table 6. interrupt control register (int) addr 7 6 5 4 3 2 1 0 0ch arst wrtc im x x x ale1 ale0 table 7. frequency out register (fo) addr7 6 5 4 3210 0dh x x x fobatb x fo2 fo1 fo0 table 8. frequency selection of f out pin frequency, f out units fo2 fo1 fo0 32768 hz 0 0 0 16372 hz 0 0 1 8192 hz 0 1 0 4096 hz 0 1 1 50/60 hz 1 0 0 1 hz101 low hz 1 1 0 high hz 1 1 1 ISL12032
16 fn6618.3 may 5, 2011 event detection register (evic) event output in battery mode enable bit (evbatb) this bit enables/disables the evdet pin during battery backup mode (i.e. vbat pin supply on). when the evbatb is set to ?1?, the event detect output is disabled in battery backup mode. when the evbatb is cleared to ?0?, the event detect output is enabled in battery backup mode. this feature can be used to save power during battery mode. event output pulse mode (evim) this bit controls the evdet pin output mode. with evim = 0, the output is in normal mode and when an event is triggered, the output will be set low until reset. with evim = 1, the output is in pulse mode and when an event is triggered, the device will generate a 200ms to 300ms pulse at the evdet output. event detect enable (even) this bit enables/disables the event detect function of the ISL12032. when this bit is set to ?1?, the event detect is active. when this bit is cleared to ?0?, the event detect is disabled. event time-based hysteresis (ehys1, ehys0) these bits set the amount of ti me-based hysteresis that is present at the evin pin for deglitching the input signal. the settings vary from 0ms (hyster esis off) to 31.25ms (delay of 31.25ms to check for change of state at the evin pin). the hysteresis function and the event input sampling function work independently. event input sampling rate (esmp) these bits set the frequency of sampling of the event input (evin). the settings include from 1/4hz (one sample per 4s) to 2hz (twice a second), 1h z, or continuous sampling (always on). the less frequent the sampling, the lower the current drain, which can affect battery current drain and battery life. . event index register (evix) the event index register provides the index for locating an individual event that has been stored. the event recording function allows recalling up to 4 events, although the event counting register will count up to 255 events. the 0th location corresponds to the first event, and the 1st through 3rd locations correspond to the most recent events, with the 3rd location (11b) representing the latest event. therefore, setting evix to 03h location and reading the tsevt section will access the timestamp information for the most recent (latest) event. setting this register to another value will allow reading the corresponding even t from the tsevt section. event bit (evix <1:0>) these bits are the event counter register index bits. evix1 is the msb and evix0 is the lsb. trickle charge register (trick) the trickle charge function allows charging current to flow from the v dd supply to the vbat pin through a selectable current limiting resistor. disabling the trickle charge function removes this connection and isolates the battery from the v dd supply in the case charging is not necessary or harmful (as in the case with a lithium coin cell battery). note that there is no charging diode in series with the trickle charge resistor, but a switch network that adds a small series resistance to the charging resistance. trickle charge bit (trken) this bit enables/disables the trickle charge capability for the backup battery supply. setting this bit to ?1? will enable the trickle charge. resetting this bit to ?0? will disable the trickle charge function and isolate the battery from the v dd supply. trickle charge resi stor (trkro<1:0>) these bits allow the user to change the trickle charge resistor settings a ccording to the maximum current desired for the battery or super capacitor charging. table 9. event detection register (evic) addr 7 6 5 4 3 2 1 0 0eh x evbatb evim even ehys1 ehys0 esmp1 esmp0 table 10. event time-based hysteresis ehsys1 ehsys0 time (ms) 00 0 013.9 1 0 16.625 1 1 31.25 table 11. event input sampling rate esmp1 esmp2 sampling rate 00 always on 01 2 hz 10 1 hz 1 1 1/4 hz table 12. event index register (evix) addr 7 6 5 4 3 2 1 0 0fh x x x x x x evix1 evix0 table 13. trickle charge register (trick) addr 7 6 5 4 3 2 1 0 10h x x x x x trken trkro1 trkro0 ISL12032
17 fn6618.3 may 5, 2011 where the r out is the selected resistor between v dd and vbat. table 14 gives the typical resistor values for v dd = 5v and vbat = 3.0v. note that the resistor value changes with v dd input voltage and vbat voltage, as well as with temperature. power supply control register (pwrvdd) clear time stamp bit (clrts) this bit clears both the time stamp v dd to battery (tsv2b) and time stamp battery to v dd (tsb2v) sections. the default setting is ?0? which allows normal operation. setting clrts = 1 performs the clear timestamp register function at the conclusion of a succ essful write operation. i 2 c in battery mode (i2cbat) this bit allows i 2 c operation in battery backup mode (vbat powered) when set to ?1?. when reset to ?0?, the i 2 c operation is disabled in battery mode, which results in the lowest i dd current. note that when the i 2 c operation is desired in vbat mode, the scl and sda pull-ups must go to the vbat source for proper communications. this will result in additional vbat current drain (on top of the increased device vbat current) during serial communications. v dd brownout trip voltage (vddtrip <2:0>) these bits set the 6 trip levels for the v dd alarm and vbat switchover. the lvdd bit in the srdc is set to ?1? when v dd drops below this preset level. see table 16. battery voltage warning register (pwrvbat) this register controls the tr ip points for the two vbat warnings, with levels set to approximately 85% and 75% of the nominal battery level. vbat hysteresis (bhys) this bit enables/disables the hysteresis voltage for the v dd /vbat switchover. when set to ?1?, hysteresis is enabled and switching to vbat occurs at approximately 50mv below the v dd trip point (set by vddt rip<2:0>). switching from vbat to v dd power will occur at approximately 50mv above the v dd trip point. when set to ?0?, there is no hysteresis and switchover will occur at exactly the vdd trip point. note that for slow moving v dd power-down and power-up signals there can be some extra switching cycles without hysteresis. battery level monitor tr ip bits (vb85tp <2:0>) three bits selects the first alarm (85% of nominal vbat) level for the battery voltage monitor. there are total of 7 levels that could be selected for the first warning. any of the levels could be selected as the first warning with no reference as to nominal vbat voltage level. see table 18 for typical values. table 14. resistor selection register trkro1 trkro0 rtrk units 0 0 1300 0 1 2200 1 0 3600 1 1 7800 table 15. power supply control register (pwrvdd) addr 7 6 5 4 3 2 1 0 11h clrts x i2cbat lvenb x vdd trip2 vdd trip1 vdd trip0 table 16. vdd trip levels v dd trip2 v dd trip1 v dd trip0 trip voltage (v) 0 0 0 2.295 0 0 1 2.550 0 1 0 2.805 i max v dd v bat ? r out -------------------------------- - = (eq. 1) 0 1 1 3.060 1 0 0 4.250 1 0 1 4.675 table 17. battery voltage warning register (pwrvbat) addr 7 6 5 4 3 2 1 0 12h x bhys vb85t p2 vb85t p1 vb85t p0 vb75t p2 vb75t p1 vb75t p0 table 16. vdd trip levels v dd trip2 v dd trip1 v dd trip0 trip voltage (v) ISL12032
18 fn6618.3 may 5, 2011 battery level monitor tr ip bits (vb75tp <2:0>) three bits selects the second warning (75% of nominal vbat) level for the battery voltage monitor. there are total of 7 levels that could be selected for the second monitor. any of the levels could be selected as the second alarm with no reference as to nominal vbat voltage level. see table 19 for typical values. ac register (ac) this register sets the performance screening for the ac input. ac 50/60hz input select (ac5060) this bit selects either 50hz or 60hz powerline ac clock input frequency. setting this bit to ?0? selects a 60hz input (default). setting this bit to ?1? selects a 50hz input. ac enable (acenb) this bit will enable/disable the ac clock input. setting this bit to ?0? will enable the ac clock input (default). setting this bit to ?1? will disable the ac clock input. when the ac input is disabled, the crystal oscillator becomes the sole source for rtc and f out clocking. ac recovery period (acrp<1:0>) this bit sets the ac clock input validation recovery period. after the ac input fails validation (acfail = 1), a predefined period is used to test the frequency and voltage of the ac clock input. the range is from 2s to 16s. ac failure cycl es (acfp<1:0>) these two bits dete rmine how many ac cycles are used for the ac clock qualification, or to disable the ac clock qualification. the range is from 1 ac cycle to 12 ac cycles or disable, and is also dependent on the ac5060 bit setting (see table 22). the qualification logic will count the number of crystal cycles in the chosen ac period, and if the count is outside the window set by acfc bits then the acfail signal is set to ?1?. for example, if 10 cycles are chosen for 50hz input, then during those 10 cycles there would need to be exactly 6554 crystal cycles. that number is subtracted from the actual count during the 10 ac cycles and the absolute value is compared to the error value se t by acfc. if the error were 10 crystal cycles and acfc we re set to 11b, then the allowable error would be 20 cr ystal cycles and the acfail would be ?0?, or qualification has passed. if the actual error count were 22 cycles then the acfail would be set to ?1?, qualification has failed. . ac/crystal frequency failure criterion (acfc<1:0>) these two bits dete rmine the number of crystal cycles used for the error budget for the ac qualification (see table 24). two of the choices are for a fixed ppm criterion of 1 or 2 crystal cycles in just one ac cycle (independent of the acfp setting). the other choices are for 1 or 2 crystal cycles per ac cycle, but includes the total number of cycles set by the acfp. using the example given for the acfp bits previously mentioned: ac5060 = 1 (50hz) acfc = 11b (2 crystal cycles/ac cycle) table 18. vb85t vbat warning levels vb85tp2 vb85tp1 vb85tp0 battery alarm trip level (v) 0 0 0 2.125 0 0 1 2.295 0 1 0 2.550 0 1 1 2.805 1 0 0 3.060 1 0 1 4.250 1 1 0 4.675 table 19. vb75t vbat warning levels vb75tp2 vb75tp1 vb75tp0 battery alarm trip level (v) 0 0 0 1.875 0 0 1 2.025 0 1 0 2.250 0 1 1 2.475 1 0 0 2.700 1 0 1 3.750 1 1 0 4.125 table 20. ac register addr 7 6 5 4 3 2 1 0 13h ac5060 acenb acrp1 acrp0 acfp1 acfp0 acfc1 acfc0 table 21. ac recovery period acrp1 acrp0 recovery time 002s 014s 108s 1 1 16s table 22. ac failure cycles cycle used for count acfp1 acfp0 ac5060 = 0 ac5060=1 (disabled) 0 0 1101 6510 12 10 1 1 ISL12032
19 fn6618.3 may 5, 2011 acfp = 11b (10 total ac cycles) so the resulting crystal cycle count must be within: (10 ac cycles x 2 crystal cycles/ac cycle) or 20 total crystal cycles (error budget) as shown in table 23. fine trim compensation register (ftr) this register (table 24) prov ides control of the crystal oscillator clock compensation and the ac clock input minimum level detect. ac minimum (acmin) this bit determines the minimum peak-to-peak voltage level for the ac clock input as a percentage of the existing v dd supply. acmin = 0 sets the minimum level to 5% x v dd . acmin = 1 sets the mini mum level to 10% x v dd . digital trim register (xdtr<3:0>) the digital trim register bits control the amount of trim used to adjust for the crystal clock e rror. this trim is accomplished by adding or subtracting the 32khz clock in the clock counter chain to adjust the rtc clock. calibration can be done by monitoring the f out pin with a frequency counter with the frequency output set to 1.0hz, with no ac input. dst control registers (dstcr) 8 bytes of control registers have been assigned for the daylight savings time (dst) functions. dst beginning (set forward) time is controlled by the registers dstmofd, dstdwfd, dstdtfd, and dsthrfd. dst ending time (set backward or reverse) is controlled by dstmorv, dstdwrv, dstdtrv and dsthrrv. tables 26 and 27 describe the st ructure and functions of the dstcr. dst forward registers (15h to 18h) dste is the dst enabling bit located in bit 7 of register 15h (dstmofdxx). set dste = 1 wil l enable the dste function. upon powering up for the first time (including battery), the dste bit defaults to ?0?. dst forward is controlled by the following dst registers: dstmofd sets the month that dst starts. the default value for the dst begin month is april (04h) . dstdwfd sets the day of t he week that dst starts. dstdwfde sets the priority of the day of the week over the date. for dstdwfde = 1, day of the week is the priority. note that day of the week coun ts from 0 to 6, like the rtc registers. the default for the dst forward day of the week is sunday (00h). dstdtfd controls which date dst begins. the default value for dst forward date is on the first date of the month (01h). dstdtfd is only effective if dstdwfde = 0. table 23. ac/crystal frequency failure criterion acfc1 acfc0 criterion total xtal cycle error budget 0 0 1 crystal cycle per ac cycle acfp x 1 0 1 2 crystal cycle per ac cycle acfp x 2 1 0 1 crystal cycle in all ac cycles 1 1 1 2 crystal cycles in all ac cycles 2 table 24. fine trim compensation register addr76543210 14h x x x acmin xdtr3 xdtr2 xdtr1 xdtr0 table 25. xdtr frequency compensation xdtr3 xdtr2 xdtr1 xdtr0 frequency compensation (ppm) 0000 0 0001 10 0010 20 0011 30 0100 40 0101 50 0110 60 0111 0 1000 0 1001 -10 1010 -20 1011 -30 1100 -40 1101 -50 1110 -60 1111 0 ISL12032
20 fn6618.3 may 5, 2011 dsthrfd controls the hour that dst begins. it includes the mil bit, which is in the corresponding rtc register. the rtc hour and dsthrfd registers need to match formats (military or am/pm) in order for the dst function to work. the default value for dst hour is 2:00am (02h). the time is advanced from 2:00:00am to 3:00:00am for this setting. dst reverse registers (19h to 1ch) dst end (reverse) is controlled by the following dst registers. dstmorv sets the month that dst ends. the default value for the dst end mont h is october (10h). dstdwrv controls the day of the week that dst should end. the dwrve bit sets the priority of the day of the week over the date. for dwrve = 1, day of the week is the priority. note that day of the week counts from 0 to 6, like the rtc registers. the default for dst dwrv end is sunday (00h). dstdtrv controls which date dst ends. the default value for dst date reverse is on the first date of the month. the dstdtrv is only effective if the dwrve = 0. dsthrrv controls the hour that dst ends. it includes the mil bit, which is in the corresponding rtc register. the rtc hour and dsthrrv registers need to match formats (military or am/pm) in order for the dst function to work. the default value sets the dst end at 2:00am. the time is set back from 2:00:00am to 1:00:00am for this setting. alarm registers (1dh to 28h) the alarm register bytes are set up identical to the rtc register bytes, except that th e msb of each byte functions as an enable bit (enable = ?1?). these enable bits specify which alarm registers (seconds, minu tes, etc.) are used to make the comparison. note that there is no alarm byte for year. the alarm function works as a comparison between the alarm registers and the rtc registers. as the rtc advances, the alarm will be triggered once a match occurs between the alarm registers an d the rtc registers. any one alarm register, multiple registers, or all registers can be enabled for a match. there are two alarm operation modes: single event and periodic interrupt mode: single event mode is enabled by setting either ale0 or ale1 to 1, then setting bit 7 on any of the alarm registers (esca... edwa) to ?1?, and setting the im bit to ?0?. this mode permits a one-time match between the alarm registers and the rtc registers. once this match occurs, the alm bit is set to ?1? and the irq output will be pulled low and will remain low until the alm bit is reset. this can be done manually or by using the auto -reset feature. since the irq output is shared by both alarms, they both need to be reset in order for the irq output to go high. interrupt mode is enabled by setting either ale0 or ale1 to 1, then setting bit 7 on any of the alarm registers (esca... edwa) to ?1?, and setting the im bit to ?1?. sett ing the im bit to 1 puts both alm0 and alm1 into interrupt mode. the irq output will now be pulsed each time an alarm occurs (either al0 or al1). this means that once the interrupt mode alarm is set, it will continue to alarm until it is reset. to clear a single event alarm, the corresponding alm0 or alm1 bit in the srdc register must be set to ?0? with a write. note that if the arst bit is set to ?1? (address 0ch, bit 7), the alm0 and alm1 bits will automatically be cleared when the status register is read. the irq output will be set by an alarm match for either alm0 or alm1. following are examples of both single event and periodic interrupt mode alarms. table 26. dst forward registers address function 7 6 5 4 3 2 1 0 15h month forward dste 0 0 mofd20 mofd13 mofd12 mofd11 mofd10 16h day forward 0 dwfde wkfd12 wkfd11 wkfd10 dwfd12 dwfd11 dwfd10 17h date forward 0 0 dtfd21 dtfd20 dtfd13 dtfd12 dtfd11 dtfd10 18h hour forward hrfdmil 0 hrfd21 hrfd20 hrfd13 hrfd12 hrfd11 hrfd10 table 27. dst reverse registers address name 7 6 5 4 3 2 1 0 19h month reverse 0 0 0 morv20 morv13 morv12 morv11 morv10 1ah day reverse 0 dwrve wkrv12 wkrv11 wkrv10 dwrv12 dwrv11 dwrv10 1bh date reverse 0 0 dtrv21 dtrv20 dtrv13 dtrv12 dtrv11 dtrv10 1ch hour reverse hrrvmil 0 hrrv21 hrrv20 hrrv13 hrrv12 hrrv11 hrrv10 ISL12032
21 fn6618.3 may 5, 2011 example 1 ? alarm set with single interrupt (im = ?0?) ? a single alarm will occur on january 1 at 11:30am. ? set alarm registers as follows: after these registers are set, an alarm will be generated when the rtc advances to exactly 11 :30 a.m. on january 1 (after seconds changes from 59 to 00) by setting the alm0 bit in the status register to ?1? and also bringing the irq output low. example 2 ? pulsed interrupt once per minute (im = ?1?) ? interrupts at one minute intervals when the seconds register is at 30 seconds. ? set alarm registers as follows: once the registers are set, the following waveform will be seen at irq : note that the status register alm0 bit will be set each time the alarm is triggered, but does not need to be read or cleared. time stamp v dd to battery registers (tsv2b) the tsv2b section bytes are identical to the rtc register section, except they do not extend beyond the month. the time stamp captures the first v dd to battery voltage transition time, and will not update upon subsequent events, until cleared (only the first event is captured before clearing). set clrts = 1 to clear this register (addr 11h, pwrvdd register). time stamp battery to v dd registers (tsb2v) the time stamp battery to v dd section bytes are identical to the rtc section bytes, e xcept they do not extend beyond month. the time stamp captur es the last transition of vbat to v dd (only the last power up event of a series of power up/down events is retained). set clrts = 1 to clear this register (addr 11h, pwrvdd register). time stamp event registers (tsevt) the tsevt section bytes are id entical to th e rtc section bytes, except they do not extend beyond the month. the time stamp captures the first even t and the most recent three events. the first event time stam p will not update until cleared. all 4 time stamps are all cleared to ?0? when writing the event counter (0bh) is set to ?0?. note: the time stamp registers are cleared to all ?0?, including the month and day, wh ich is different from the rtc and alarm registers (those regist ers default to 01h). this is the indicator that no time stamping has occurred since the last clear or initial power-up. once a time stamp occurs, there will be a non-zero time stamp. user memory registers (accessed by using slave address 1010111x) addresses [00h to 7fh] these registers are 128 bytes of battery-backed user sram. writes to this section do not need to be proceeded by setting the wrtc bit. i 2 c serial interface the ISL12032 supports a bi-directional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is the master and the device being controlled is the slave. the master always initiates data transfers and provides the clock for both transmit and receive o perations. therefore, the ISL12032 operates as a slave device in all applications. all communication over the i 2 c interface is conducted by sending the msb of each byte of data first. alarm register bit description 76543210hex sca0 00000000 00hsec onds disabled mna0 10110000 b0hminutes set to 30, enabled hra0 10010001 91hhours set to 11, enabled dta0 10000001 81hdate set to 1, enabled moa0 10000001 81hmonth set to 1, enabled dwa0 00000000 00hday of week disabled alarm register bit description 76543210hex sca0 10110000b0hseconds set to 30, enabled mna0 00000000 00hminutes disabled hra0 00000000 00hhours disabled dta0 00000000 00hdate disabled moa0 00000000 00hmonth disabled dwa0 00000000 00hday of week disabled 60s rtc and alarm registers are both ?30s? figure 5. irq waveform ISL12032
22 fn6618.3 may 5, 2011 protocol conventions data states on the sda line can change only during scl low periods. sda state cha nges during scl high are reserved for indicating start and stop conditions (see figure 6). on power-up of the ISL12032, the sda pin is in the input mode. all i 2 c interface operations must begin with a start condition, which is a high to low transition of sda while scl is high. the ISL12032 continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition is met (see figure 6). a start condition is ignored during the power-up sequence. all i 2 c interface operations must be terminated by a stop condition, which is a low to high transition of sda while scl is high (see figure 6). a stop condition at the end of a read operation or at the end of a write operation to memory only places the device in its standby mode. an acknowledge (ack) is a software convention used to indicate a successful data transfer. the transmitting device, either master or slave, releases the sda bus after transmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge the reception of the eight bits of data (see figure 7). the ISL12032 responds with an ack after recognition of a start condition followed by a valid identification byte, and once again after successful rece ipt of an address byte. the ISL12032 also responds with an ack after receiving a data byte of a write operation. th e master must respond with an ack after receiving a data byte of a read operation. figure 6. valid data changes, start and stop conditions figure 7. acknowledge response from receiver figure 8. byte write sequence (slave address for csr shown) sda scl start data data stop stable change data stable sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance high impedance s t a r t s t o p identification byte data byte a c k signals from the master signals from the ISL12032 a c k 10 0 11 a c k write signal at sda 0000 111 address byte ISL12032
23 fn6618.3 may 5, 2011 device addressing following a start condition, the master must output a slave address byte. the 7 msbs are the device identifier. these bits are ?1101111b? for the rtc registers and ?1010111b? for the user sram. the last bit of the slave address byte defines a read or write operation to be performed. when this r/w bit is a ?1?, then a read operation is selected. a ?0? selects a write operation (refer to figure 9). after loading the entire slave address byte from the sda bus, the ISL12032 compares the device identifier and device select bits with ?1101111b? or ?1010111b?. upon a correct compare, the device outputs an acknowledge on the sda line. following the slave byte is a one byte word address. the word address is either supplied by the master device or obtained from an internal counter. on power up the internal address counter is set to address 00h, so a current address read starts at address 00h. when required, as part of a random read, the master must supply the 1 word address byte as shown in figure 9. in a random read operation, the slave byte in the ?dummy write? portion must match the slave byte in the ?read? section. for a random read of the control/stat us registers, the slave byte must be ?1101111x? in both places. write operation a write operation requires a star t condition, followed by a valid identification byte, a valid address byte, a data byte, and a stop condition. after each of the three bytes, the ISL12032 responds with an ack. at this time, the i 2 c interface enters a standby state. a multiple byte operation within a page is permitted. the address byte must have the start address, and the data bytes are sent in sequence af ter the address byte, with the ISL12032 sending an ack after each byte. the page write is terminated with a stop condition from the master. the pages within the ISL12032 do not support wrapping around for page read or write operations. read operation a read operation consists of a three byte instruction followed by one or more data bytes (see figure 10). the master initiates the operation issuing the following sequence: a start, the identification byte with the rw bit set to ?0?, an address byte, a second start, and a second identification by te with the rw bit set to ?1?. after each of the three bytes, the ISL12032 responds with an ack. then the ISL12032 transmits data bytes as long as the master responds with an ack during the scl cycle following the eighth bit of each byte. the master terminates the read operation (issuing a stop condit ion) following the last bit of the last data byte (see figure 10). the data bytes are from the memory location indicated by an internal pointer. this pointers initial value is determined by the address byte in the read operation instruction, and increments by one during transmission of each data byte. after reaching the last memory location in a section or page, the master should issue a stop. bytes that are read at addresses higher than the last address in a section may be erroneous. figure 9. slave address, word address, and data bytes slave address byte d7 d6 d5 d2 d4 d3 d1 d0 a0 a7 a2 a4 a3 a1 data byte a6 a5 1 10 1 1 1 r/w 1 word address signals from the master signals from the slave signal at sda s t a r t identification byte with r/w =0 address byte a c k a c k 0 s t o p a c k 1 identification byte with r/w = 1 a c k s t a r t last read data byte first read data byte a c k 10 1 1111 10 1 11 11 figure 10. read sequence (csr slave address shown) ISL12032
24 fn6618.3 may 5, 2011 application section oscillator crys tal requirements the ISL12032 uses a standard 32.768khz crystal. either through hole or surface mount crystals can be used. table 28 lists some recommended surface mount crystals and the parameters of each. this list is not exhaustive and other surface mount devices can be used with the ISL12032 if their specifications are very similar to the devices listed. the crystal should have a required parallel load capacitance of 12.5pf and an equivalent series resistance of less than 50k . the crystal?s temperature range specification should match the application. many crystals are rated for -10c to +60c (especially through hole and tuning fork types), so an appropriate crystal should be selected if extended temperature range is required. layout considerations the crystal input at x1 has a very high impedance, and oscillator circuits operati ng at low frequencies (such as 32.768khz) are known to pick up noise very easily if layout precautions are not followed. most instances of erratic clocking or large accuracy errors can be traced to the susceptibility of the oscillator circuit to interference from adjacent high speed clock or data lines. careful layout of the rtc circuit will avoid noise pickup and ensure accurate clocking. two main precautions for crystal pc board layout should be followed: 1. do not run the serial bus lines or any high speed logic lines in the vicinity of the crystal. these logic level lines can induce noise in the oscillator circuit to cause misclocking. 2. add a ground trace around the crystal with one end terminated at the chip gr ound. this will provide termination for emitted noise in the vicinity of the rtc device. in addition, it is a good idea to avoid a ground plane under the x1 and x2 pins and the crystal, as this will affect the load capacitance and therefore the oscillator accuracy of the circuit. if the f out pin is used as a clock, it should be routed away from the rtc device as well. the traces for the vbat and v dd pins can be treated as a ground, and should be routed around the crystal. ac input circuits the ac input ideally will have a 2.5v p-p sine wave at the input, so this is the target for any signal conditioning circuitry for the 50/60hz waveform. no te that the peak-to-peak amplitude can range from 1v p-p up to v dd , although it is best to keep the max si gnal level just below v dd . the ac input provides dc offset so ac coupling with a series capacitor is advised. if the ac power supply has a transformer, the secondary output can be used for clocking with a resistor divider and series ac coupling capacitor. a sample circuit is shown in figure 12. values for r 1 /r 2 are chosen depending on the peak-to-peak range on the secondary voltage in order to match the input of the ISL12032. c in can be sized to pass up to 300hz or so, and in most cases, 0.47f should be the selected value for a 20% tolerance device. the ac input to the is12032 ca n be damaged if subjected to a normal ac waveform when v dd is powered down. this can happen in circuits where there is a local ldo or power switch for placing circuitry in standby, while the ac main is still switched on. figure 11 shows a modified version of the figure 12 circuit, which uses an emitter follower to essentially turn off the ac input waveform if the v dd supply goes down. using the ISL12032 with no ac input some applications may need all the features of the ISL12032 but do not have access to the power line ac clock, or do not need the accuracy prov ided by that clock. in these cases there is no problem using the crystal oscillator as the primary clock source for the device. the user must simply set the acenb bit in register 13h to ?1?, which disables the ac input pin and forces the device to use the crystal oscillator exclusively for the rtc and f out clock source. setting this bit to ?1? also will cause the acrdy bit in the srac register to be set to ?1?, indicating that there can be no fault with th e ac input clock since it is not used. table 28. suggested surface mount crystals manufacturer part number citizen cm200s epson mc-405, mc-406 raltron rsm-200s saronix 32s12 ecliptek ecpsm29t-32.768k ecs ecx-306 fox fsm-327 ISL12032
25 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6618.3 may 5, 2011 . figure 11. ac input using a transformer secondary ISL12032 120vac 50/60hz vin (ac) = 1.5v p-p to vdd (max) r1 r2 cin figure 12. using the v dd supply to gate the ac input ISL12032 120vac 50/60hz vin (ac) = 1.5v p-p to vdd (max) r1 r2 cin vdd c1 ISL12032
26 fn6618.3 may 5, 2011 ISL12032 package outline drawing m14.173 14 lead thin shrink small outline package (tssop) rev 3, 10/09 detail "x" side view typical recommended land pattern top view b a 17 8 14 c plane seating 0.10 c 0.10 c b a h pin #1 i.d. mark 5.00 0.10 4.40 0.10 0.25 +0.05/-0.06 6.40 0.20 c b a 0.05 0-8 gauge plane see 0.90 +0.15/-0.10 0.60 0.15 0.09-0.20 5 2 3 1 3 1.00 ref 0.65 1.20 max 0.25 0.05 min 0.15 max (1.45) (5.65) (0.65 typ) (0.35 typ) detail "x" 1. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. dimension does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 per side. 3. dimensions are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m-1994. 5. dimension does not include dambar protrusion. allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. minimum space between protrusion and adjacent lead is 0.07mm. 6. dimension in ( ) are for reference only. 7. conforms to jedec mo-153, variation ab-1. notes: end view

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